The present invention relates to a method for manufacturing a capacitor for a semiconductor memory device, and particularly to a method for manufacturing a capacitor for a semiconductor memory device with increased cell capacitance.
Reduced memory cell area can lead to decreased cell capacitance, which is a serious obstacle to increasing the packing density of a dynamic random access memory (DRAM). Decreased cell capacitance results in degraded read-out capability, an increase in the soft error rate of the memory cell, excessive power consumption during low voltage operation. Thus, increasing unit area cell capacitance is desirable in order to increase packing density.
Recently, many methods for increasing cell capacitance have been proposed, which generally relate to either improving the structure of the capacitor storage electrode or changing the characteristics of the storage electrode material. An example of a method of the first type involves increasing the effective capacitor area by forming a storage electrode having a three-dimensional structure, e.g., a cylindrical structure.
FIGS. 1 through 4 are cross-sectional views illustrating a conventional method for manufacturing a cylindrical storage electrode having a bar electrode therein, as disclosed in U.S. patent application Ser. No. 07/917,182.
Referring to FIG. 1, a pair of transistors each having a source region 14 and a gate electrode 18 and commonly sharing a drain region 16 and a bit line 20 are formed on the active region of a semiconductor substrate 10. Substrate 10 is divided into active and isolation regions by a field oxide 12. Insulating layer 19 is formed on the entire surface of the resultant structure for insulating the transistors. Planarizing layer 40 is formed for planarizing the surface of substrate 10, and silicon nitride (Si.sub.3 N.sub.4) is deposited to a thickness of 30.about.300 .ANG. on planarizing layer 40 to form an etch-blocking layer 42. An oxide is deposited to a thickness of about 1,000 .ANG. on etch-blocking layer 42 to form sacrificial layer 44. Then, sacrificial layer 44, etch-blocking layer 42, planarizing layer 40 and insulating layer 19 are selectively removed to form a contact hole (not shown). Thereafter, a conductive material, e.g., an impurity-doped polycrystalline silicon, is deposited on the entire surface of the resultant structure, to form first conductive layer 50 having a thickness of about 5,000 .ANG. and filling the contact hole. An oxide and a polycrystalline silicon are sequentially deposited on first conductive layer 50, each to a thickness of about 500 .ANG., to form oxide film 52 and second conductive layer 54, respectively.
Referring to FIG. 2, storage electrode pattern 54a is formed by patterning second conductive layer 54 according to a photo-lithography process, and oxide film 52 is wet-etched to thereby form bar electrode etch-mask 52a. Thereafter, polycrystalline silicon is deposited to a thickness of about 1,000 .ANG. on the entire surface of the resultant structure to form a third conductive layer 56, and an oxide is deposited to a thickness of about 1,000 .ANG. on third conductive layer 56. Then, the oxide film is anisotropically etched to form spacer 58 on the sloped side portions of third conductive layer 56.
Referring to FIG. 3, an anisotropic etching process is performed on the entire surface of the resultant structure of FIG. 2, using spacer 58 and etch-mask 52a as a mask and using sacrificial layer 44 as an etch-end point, to form storage electrode 100 composed of bar electrode 100a and cylindrical electrode 100b.
Referring to FIG. 4, after removing spacer 58, etch-mask 52a and sacrificial layer 44 by a wet etching process, a high dielectric material is coated on the entire surface of storage electrode 100, to thereby form dielectric film 110. Then, a conductive material, e.g., an impurity-doped polycrystalline silicon, is deposited on dielectric film 110 to form plate electrode 120. Resulting capacitors C1 and C2 are composed of storage electrode 100, dielectric film 110 and plate electrode 120.
This conventional method is simple and has a large process margin. However, storage electrode height is limited due to the step-difference problem in the subsequent metallization process. Accordingly, the cell capacitance required for highly integrated semiconductor memory devices (256 Mb and higher) cannot be realized using this method.